A RAM is used for storing programs or data created by a user, and is classified as an SRAM and a DRAM. The SRAM is a random access memory which has memory cell(s) operating in a flip-flop way, and it is usually used for a low capacity memory or a cache memory because it keeps memorizing the contents stored therein without a complicated refresh clock as long as a power supply is provided. The speed of the SRAM is rapider than that of the DRAM around 5 times and the SRAM is more expensive than the DRAM. The SRAM includes a flip-flop memory cell which is comprised of four to six MOSFETs and the operation mechanism of the SRAM is same as that of a conventional flip-flop. The power consumption per one bit of the SRAM is lower than that of the DRAM.
The SRAM is classified as a full CMOS cell, a HRL (high resist load) cell and a TFT cell according to a cell structure.
The full CMOS cell is formed with six transistors in its bulk region. The full CMOS cell has merits in that it can be operated in a high speed with a low power consumption, while it has demerits in that a large scale integration is unfavorable.
The HRL cell is comprised of four transistors and two resistances. The HRL cell has merits in that its fabricating process is simple and a large scale integration is favorable, while it has demerits in that it has a high stand-by electric current and a low soft error resistance.
The TFT cell has a structure that a poly TFT is laminated on a MOSFET. The TFT cell has merits in that it has an appropriate stand-by electric current and a large scale integration is favorable, while it has demerits in that it has a high power consumption.
FIG. 1 illustrates a conventional method for fabricating the SRAM having a TFT cell structure, and a region illustrated in FIG. 1 corresponds to a part of a cell array of the SRAM.
FIG. 1(a) shows a step for forming the MOSFET, which is used in later for laminating poly TFT thereon. The MOSFET is comprised of a gate 11 and a source/drain 12 which is formed on a silicon wafer 10 serving as a semiconductor substrate. The detailed explanation about the formation of the MOSFET is omitted.
FIG. 1(b) shows a step for forming seed layer which is used for fabricating polysilicon. The polysilicon is usually fabricated by crystallizing amorphous silicon by using singlecrystalline silicon as a seed.
First, an interlayer insulating layer 13 is formed on the MOSFET, and then contact holes 14 are formed through the interlayer insulating layer 13, thereby exposing the region of the source/drain 12.
Then, the seed layer, i.e., the singlecrystalline silicon layer 15 is formed in the contact holes 14 by using SEG (selective epitaxial growth) technique. The SEG technique is a sort of a chemical vapor deposition technique, capable of making single-crystalline silicon grow only in the region where silicon is exposed by using gas such as SiH4 and H2 at the temperature over 900° C. That is, singlecrystalline silicongrows only on the source/drain 12 (because it is made of silicon), which is exposed through the contact holes 14, while it does not grow in the interlayer insulating layer 13.
FIG. 1(c) shows a step for forming an amorphous silicon layer 16 on the interlayer insulating layer 13 and the singlecrystalline silicon layer 15. The amorphous silicon layer 16 may be usually formed by using LPCVD (low pressure chemical vapor deposition) or PECVD (plasma enhanced chemical vapor deposition).
FIG. 1(d) shows a step for forming a polysilicon layer 17 through a heat treatment of the amorphous silicon layer 16, wherein the singlecrystalline siliconlayer 15 functions as a seed for crystallization of the amorphous silicon. Then, the poly TFT is fabricated on the polysiliconlayer 17, resulting in the SRAM. The detailed explanation thereabout is omitted.